The invention generally relates to semiconductor manufacturing and, more particularly, to wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps.
Stacked chips may be used to increase the function that can be provided by a single package. The constituent chips of the chip stack are arranged in a compact three-dimensional stack characterized by multiple levels. The functionality of a chip stack requires functionality of each individual chip. The stacked arrangement of the three-dimensional integration conserves space and shortens signal transmission distances for inter-chip communications, which may improve both efficiency and performance of the chip stack. During manufacture, each chip is processed independently to form integrated circuits. The different chips are subsequently stacked in a three-dimensional arrangement and bonded so that the chips are vertically arranged with permanent attachment to each other.
Signals and power must be transmitted to all silicon chips in the chip stack. One approach is to provide a conductor that penetrates from one side of a chip or interposer to the opposite side of the chip or interposer. Such conductors are often called through-substrate vias (TSVs). One way of stacking the chips is by using solder bumps between the chips, which are used in conjunction with the TSVs to distribute power and signals.
Improved wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps are needed.